Delay-insensitive ternary logic (DITL)

Author

Ravi Sankar Parameswaran Nair

Keywords and Phrases

NULL Convention Logic

Abstract

"This thesis focuses on development of a Single Rail Ternary Voltage Delay-Insensitive paradigm called Delay-Insensitive Ternary Logic (DITL), which is based on NULL Convention Logic (NCL). Single rail asynchronous logic has potential advantages over Dual-Rail logic such as reduction of Power and Interconnect as well as Logic Area. The DITL concept is developed in steps of individual circuit components. These components are designed at the transistor level and are connected together to form a registered pipeline system. Some variations in pipeline design are also investigated"--Abstract, page iii.

Advisor(s)

Smith, Scott C.

Committee Member(s)

Al-Assadi, Waleed K.
Beetner, Daryl G.

Department(s)

Electrical and Computer Engineering

Degree Name

M.S. in Computer Engineering

Sponsor(s)

National Science Foundation (U.S.)

Publisher

University of Missouri--Rolla

Publication Date

Fall 2007

Pagination

viii, 57 pages

Rights

© 2007 Ravi Sankar Parameswaran Nair, All rights reserved.

Document Type

Thesis - Open Access

File Type

text

Language

English

Subject Headings

Asynchronous circuits -- Design and constructionElectronic circuit designLogic circuits -- Design and construction

Thesis Number

T 9271

Print OCLC #

233832330

Electronic OCLC #

182540108

Recommended Citation

Parameswaran Nair, Ravi Sankar, "Delay-insensitive ternary logic (DITL)" (2007). Masters Theses. 4568.
https://scholarsmine.mst.edu/masters_theses/4568