Generic algorithms and NULL Convention Logic hardware implementation for unsigned and signed quad-rail multiplication

Author

Samarsen Reddy Mallepalli

Keywords and Phrases

NULL Convention Logic

Abstract

"This thesis focuses on designing generic quad-rail arithmetic circuits, such as signed and unsigned multipliers and Multiply and Accumulate (MAC) units, using the asynchronous delay-insensitive NULL Convention Logic (NCL) paradigm. This work helps to build a library of reusable components to be used for automated NCL circuit synthesis, which will aid in the integration of asynchronous design paradigms into the semiconductor industry"--Abstract, page iii.

Advisor(s)

Smith, Scott C.

Committee Member(s)

Al-Assadi, Waleed K.
Beetner, Daryl G.

Department(s)

Electrical and Computer Engineering

Degree Name

M.S. in Computer Engineering

Sponsor(s)

National Science Foundation (U.S.)

Publisher

University of Missouri--Rolla

Publication Date

Fall 2007

Pagination

ix, 68 pages

Note about bibliography

Includes bibliographical references (pages 55-56).

Rights

© 2007 Samarsen Reddy Mallepalli, All rights reserved.

Document Type

Thesis - Open Access

File Type

text

Language

English

Subject Headings

Asynchronous circuits -- Design and constructionElectronic circuit designLogic circuits -- Design and construction

Thesis Number

T 9265

Print OCLC #

233708544

Electronic OCLC #

182540541

Recommended Citation

Mallepalli, Samarsen Reddy, "Generic algorithms and NULL Convention Logic hardware implementation for unsigned and signed quad-rail multiplication" (2007). Masters Theses. 4565.
https://scholarsmine.mst.edu/masters_theses/4565