A Hardware-In-Loop test bed for WIMAX downlink baseband processing using Simulink and field programmable gate arrays

Author

Sarat Kumar Chitneni

Abstract

"A Hardware-In-Loop (HIL) approach involves using an embedded system such as an FPGA as a simulation device in a software environment such as Simulink. This accelerates the simulation time and also aids in rapid system prototyping for building a complete hardware model based on software algorithm design. A thorough study is needed to identify the design challenges that one faces in implementing a design based on this approach.

WIMAX (Worldwide Interoperability for Microwave Access) is a fast emerging technology in modem wireless communications based on IEEE 802.16 standards for broadband wireless networks. Such a system design and its optimization are generally started using modeling tools such as Simulink. However, in the transition of the design from software environment to a hardware model, a HIL approach offers greater flexibility for design and test. Downlink Baseband Processing which is a part of a WIMAX transmitter model is implemented with the HIL approach on an FPGA and the rest of the transmitter and receiver blocks are implemented in Simulink. Thus, the HIL test bed provides significant convenience and flexibility for system level testing along with accelerating design development.

Additionally, an audio filter design on FPGA which is developed for DSP curriculum in Computer Engineering using Altera’s DE2 FPGA Kits is also presented. A low pass filter is implemented on an FPGA device and its operation is tested using audio signals channeled thorough the FPGA development board’s audio codec"--Abstract, page iv.

Advisor(s)

Zheng, Y. Rosa

Committee Member(s)

Al-Assadi, Waleed K.
Beetner, Daryl G.

Department(s)

Electrical and Computer Engineering

Degree Name

M.S. in Electrical Engineering

Publisher

Missouri University of Science and Technology

Publication Date

Fall 2008

Journal article titles appearing in thesis/dissertation

• A hardware-In-Loop transceiver test bed processing using Simulink and FPGA
• DSP curriculum development for computer engineering using Altera's DE2 FPGA kits

Pagination

x, 59 pages

Note about bibliography

Includes bibliographical references.

Rights

© 2008 Sarat Kumar Chitneni, All rights reserved.

Document Type

Thesis - Restricted Access

File Type

text

Language

English

Subject Headings

Broadband communication systemsField programmable gate arraysIEEE 802.16 (Standard)SIMULINKWireless communication systems

Thesis Number

T 9429

Print OCLC #

313477338

Recommended Citation

Chitneni, Sarat Kumar, "A Hardware-In-Loop test bed for WIMAX downlink baseband processing using Simulink and field programmable gate arrays" (2008). Masters Theses. 4449.
https://scholarsmine.mst.edu/masters_theses/4449