Masters Theses
Abstract
"Current clinical body surface mapping (BSM) systems need automated, reliable data acquisition systems to quickly and easily obtain accurate potentials from many locations on the body-surface. Design of a computerized electrode array (CEA) for this purpose includes both hardware and software components. The CEA is a real-time, hardware intensive embedded system. Modeling of this hardware-software system with a well-established modeling language for software, Unified Modeling Language (UML), was attempted. UML diagrams help understand operation and design of the system being modeled, including hardware-software separation. A proposal for the hardware design of the node is made. The proposed CEA architecture consists of thirteen nodes, where each node services sixteen electrodes and all nodes communicate using ARCNET protocol. Exploration and comparison of design options is described in detail. A Bus Functional Model (BFM) in VHDL was created for the Microcontroller-ARCNET interface chip used in the node design. The BFM was integrated with other VHDL models to simulate node design. Board-level testing was done to check for timing violations and bus contentions. No damaging bus contentions or timing violations were found. The design of the node is complete and tested successfully in software. The proposed CEA should help allow quick and accurate measurement of BSMs"--Abstract, page iii.
Advisor(s)
Beetner, Daryl G.
Committee Member(s)
Pottinger, Hardy J., 1944-
McMillin, Bruce M.
Department(s)
Electrical and Computer Engineering
Degree Name
M.S. in Electrical Engineering
Publisher
University of Missouri--Rolla
Publication Date
Fall 2000
Pagination
xi, 93 pages
Note about bibliography
Includes bibliographical references (pages 90-92).
Rights
© 2000 Venkatasateesh Gudla, All rights reserved.
Document Type
Thesis - Restricted Access
File Type
text
Language
English
Thesis Number
T 7793
Print OCLC #
45666288
Electronic OCLC #
1121204768
Recommended Citation
Gudla, Venkatasateesh, "A medical instrument for body-surface mapping: UML model, hardware design, and VHDL simulation" (2000). Masters Theses. 4404.
https://scholarsmine.mst.edu/masters_theses/4404
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