Masters Theses
Development of a user friendly gate level logic simulator
Department(s)
Electrical and Computer Engineering
Degree Name
M.S. in Electrical Engineering
Publisher
University of Missouri--Rolla
Publication Date
Spring 1986
Pagination
vii, 70 pages
Rights
© 1986 Kumar Shiv, All rights reserved.
Document Type
Thesis - Citation
File Type
text
Language
English
Thesis Number
T 5353
Print OCLC #
14163129
Recommended Citation
Shiv, Kumar, "Development of a user friendly gate level logic simulator" (1986). Masters Theses. 332.
https://scholarsmine.mst.edu/masters_theses/332
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