Schematic capture design & power calculation for NULL convention delay - insensitive digital circuits using Mentor Graphics design tool suite
Keywords and Phrases
NULL Convention Logic (NCL); Schematic capture design
"This M.S. thesis is intended to familiarize the reader with the syntax and semantics of NULL Convention Logic (NCL), to develop an NCL schematic capture design entry tool in Mentor Graphics, to develop a method for measuring an NCL circuit's average power per operation in Mentor Graphics, and to develop an NCL iterative divider for use as a test circuit. The main focus will be on developing methods to utilize the Mentor Graphics design tools for asynchronous delay-insensitive digital design.--Introduction, page 1.
Electrical and Computer Engineering
M.S. in Computer Engineering
University of Missouri--Rolla
Journal article titles appearing in thesis/dissertation
- Insensitive digital circuits using Mentor Graphics design tool suite
- Schematic capture design and power calculation for NULL convention delay - insensitive digital circuits using Mentor Graphics design tool suite
viii, 70 leaves
© 2003 Sareen K. Devireddy, All rights reserved.
Thesis - Citation
Library of Congress Subject Headings
Integrated circuits -- Design and construction
Print OCLC #
Link to Catalog Record
Full-text not available: Request this publication directly from Missouri S&T Library or contact your local library.http://laurel.lso.missouri.edu/record=b5073644~S5
Devireddy, Sareen K., "Schematic capture design & power calculation for NULL convention delay - insensitive digital circuits using Mentor Graphics design tool suite" (2003). Masters Theses. 2403.
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