Schematic capture design & power calculation for NULL convention delay - insensitive digital circuits using Mentor Graphics design tool suite

Author

Sareen K. Devireddy

Keywords and Phrases

NULL Convention Logic (NCL); Schematic capture design

Abstract

"This M.S. thesis is intended to familiarize the reader with the syntax and semantics of NULL Convention Logic (NCL), to develop an NCL schematic capture design entry tool in Mentor Graphics, to develop a method for measuring an NCL circuit's average power per operation in Mentor Graphics, and to develop an NCL iterative divider for use as a test circuit. The main focus will be on developing methods to utilize the Mentor Graphics design tools for asynchronous delay-insensitive digital design.--Introduction, page 1.

Department(s)

Electrical and Computer Engineering

Degree Name

M.S. in Computer Engineering

Publisher

University of Missouri--Rolla

Publication Date

Fall 2003

Journal article titles appearing in thesis/dissertation

• Insensitive digital circuits using Mentor Graphics design tool suite
• Schematic capture design and power calculation for NULL convention delay - insensitive digital circuits using Mentor Graphics design tool suite

Pagination

viii, 70 pages

Rights

© 2003 Sareen K. Devireddy, All rights reserved.

Document Type

Thesis - Citation

File Type

text

Language

English

Subject Headings

Integrated circuits -- Design and construction
Logic circuits

Thesis Number

T 8297

Print OCLC #

54900596

Link to Catalog Record

Full-text not available: Request this publication directly from Missouri S&T Library or contact your local library.

Recommended Citation

Devireddy, Sareen K., "Schematic capture design & power calculation for NULL convention delay - insensitive digital circuits using Mentor Graphics design tool suite" (2003). Masters Theses. 2403.
https://scholarsmine.mst.edu/masters_theses/2403