Masters Theses
Abstract
"Functional verification of an ASIC has become one of the most challenging tasks due to the increased system complexity and gate count. More than half of the time consumed in development of new ICs and systems is now spent on verification. This work investigates some of the software testing methodologies that can be adopted for efficient verification of VHDL models.
The model that is to be verified is a behavioral VHDL model of the 8051 microcontroller that is being developed at the University of Missouri-Rolla. Code coverage technology, black box testing, white box testing and software fault injection are the different software testing methodologies that are used for the verification of this model. Analysis of the model was done using data flow diagrams, state diagrams, program structure charts and program flow graphs.
Enough test instructions were included at the appropriate places in the test program to increase the testability and observability of the code. The level of different types of coverage achieved by different test programs while performing verification of the model was investigated. The types of faults that were found by each of the different testing methodologies were investigated and characterized. Test vectors developed for testing this behavioral VHDL model are useful for testing the register transfer level (RTL) model and also to test the final ASIC.
Each of the different testing techniques, black box testing, white box testing and fault injection testing, was found to uncover at least one new error that was not exposed by the other two techniques. Most of the errors and much useful information for error correction were obtained during white box testing"--Abstract, page iv.
Advisor(s)
Miller, Ann K.
Committee Member(s)
Beetner, Daryl G.
McMillin, Bruce M.
Department(s)
Electrical and Computer Engineering
Degree Name
M.S. in Computer Engineering
Publisher
University of Missouri--Rolla
Publication Date
Fall 2000
Pagination
xi, 98 pages
Note about bibliography
Includes bibliographical references (pages 95-97).
Rights
© 2000 Maya Sooraj Gemini, All rights reserved.
Document Type
Thesis - Restricted Access
File Type
text
Language
English
Thesis Number
T 7791
Print OCLC #
45666041
Electronic OCLC #
1111628100
Link to Catalog Record
Electronic access to the full-text of this document is restricted to Missouri S&T users. Otherwise, request this publication directly from Missouri S&T Library or contact your local library.
http://merlin.lib.umsystem.edu/record=b4497246~S5Recommended Citation
Gemini, Maya Sooraj, "Software testing methodologies applied to verification of VHDL model of 8051 microcontroller" (2000). Masters Theses. 1944.
https://scholarsmine.mst.edu/masters_theses/1944
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