Masters Theses
Development of multi-input gate level logic and fault simulator
Department(s)
Computer Science
Degree Name
M.S. in Computer Science
Publisher
University of Missouri--Rolla
Publication Date
Fall 1983
Pagination
ix, 85 pages
Rights
© 1983 S. P. R. Amaresan, All rights reserved.
Document Type
Thesis - Citation
File Type
text
Language
English
Thesis Number
T 4979
Print OCLC #
10344169
Recommended Citation
Amaresan, S. P. R., "Development of multi-input gate level logic and fault simulator" (1983). Masters Theses. 14.
https://scholarsmine.mst.edu/masters_theses/14
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