Performance of a Quaternary Logic Design

M. Dornajafi
B. Cooper
Steve Eugene Watkins, Missouri University of Science and Technology
M. Ryan Bales

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This paper analyzes the performance of a quaternary logic circuit and its components. The multi-valued logic design consisting of two drivers and a transistor matrix is simulated using Mentor Graphic software. Functional operation of the circuit is shown and propagation delay and power consumption are determined. The design is dependent on the voltage values for the multi-valued logic. Three logic cases are investigated. The performance of the logic circuit as a quaternary difference calculator is described.