With molecular-scale materials and fabrication techniques recently developed, high-density computing systems in nanometer domain emerge. An array-based nanoarchitecture has been recently proposed based on nanowires such as carbon nanotubes (CNTs), silicon nanowires (SiNWs). High-density nanoarray-based systems consisting of nanometer-scale elements are likely to have many imperfections; thus, defect-tolerance is considered as one of the most significant challenges. In this paper, we propose a probabilistic yield model for the array-based nanoarchitecture. The proposed yield model can be used 1) to accurately estimate the raw and net array densities, and 2) to design and optimize more defect and fault-tolerant systems based on the array-based nanoarchitecture.
S. Zhang et al., "Defect Characterization and Yield Analysis of Array-Based Nanoarchitecture," Proceedings of the 4th IEEE Conference on Nanotechnology (2004, Munich, Germany), pp. 50-52, Institute of Electrical and Electronics Engineers (IEEE), Aug 2004.
The definitive version is available at https://doi.org/10.1109/NANO.2004.1392246
4th IEEE Conference on Nanotechnology (2004: Aug. 16-19, Munich, Germany)
Electrical and Computer Engineering
Keywords and Phrases
C; Si; Array-Based Nanoarchitecture; Carbon Nanotubes; Defect-Tolerance; Elemental Semiconductors; Failure Analysis; Fault Tolerance; Fault-Tolerant Systems; High-Density Computing Systems; Imperfections; Molecular-Scale Materials; Nanoelectronics; Nanometer Domain; Nanotube Devices; Nanowires; Net Array Densities; Probabilistic Yield Model; Probability; Raw Array Densities; Silicon; Silicon Nanowires; Yield Analysis
International Standard Book Number (ISBN)
Article - Conference proceedings
© 2004 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
01 Aug 2004