As the design and fabrication complexities for the instrumentation-on-silicon systems intensify, optimization of combined Built-In Self-Test (BIST) and Automated Test Equipment (ATE) testing becomes more desirable to meet the required fault-coverage while maintaining acceptable cost overhead. The cost associated with combined BIST/ATE testing of such systems mainly consists of the following; (1) the cost induced by the BIST area overhead and (2) the cost induced by the overall testing time. In general, BIST has faster testing speed than ATE, while it can provide only limited fault-coverage and driving higher fault-coverage from BIST means additional area cost overhead. On the other hand, higher fault-coverage can be usually achieved from ATE, but excessive use of ATE results in additional test time cost. Fault-coverage of BIST and ATE plays a significant role since it can affect the area overhead in BIST and test time in BIST/ATE. This paper is to propose a novel numerical method to find an optimized fault-coverage implemented in BIST and ATE so that a minimum cost can be achieved. The proposed method. then, is applied to two parallel combined BIST/ATE testing schemes to assure its technical validity.

Meeting Name

21st IEEE Instrumentation and Measurement Technology Conference: IMTC (2004: May 18-20, Como, Italy)


Electrical and Computer Engineering

Keywords and Phrases

Acceptable Cost Overhead; Area Overhead Cost; Automated Test Equipment (ATE); Automatic Test Equipment; Built-In Self Test (BIST); Combined Testing; Cost Reduction; Cost-Driven Optimization; Expected Number of Faults; Fault Coverage; Fault Diagnosis; Optimisation; Combined BIST/ATE; Optimization; Yield

International Standard Book Number (ISBN)


International Standard Serial Number (ISSN)


Document Type

Article - Conference proceedings

Document Version

Final Version

File Type





© 2004 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

01 May 2004