Abstract

This paper presents an enhanced closed-form approach for modeling and optimizing high-frequency PCB vias, implemented in Python and validated against industry standard tools such as ADS and HFSS. The model incorporates resistance alongside inductance and capacitance to capture frequency-dependent losses and integrates non-functional pads (NFPs), demonstrating significant improvements in signal integrity by reducing reflections and enhancing return loss, particularly at 100 GHz. The methodology extends the frequency range of previous models from 100 GHz to 150 GHz, ensuring compatibility with next-generation standards like PCIe Gen 6. Validation results show insertion loss deviations under 3 dB and consistent return loss across the frequency range. The Python-based implementation offers a scalable and efficient solution for multilayer via designs, significantly reducing computational time compared to HFSS. This work provides a robust framework for high-speed PCB via modeling, with applications in academic research and industry, and includes future extensions to model differential signal vias.

Department(s)

Electrical and Computer Engineering

Comments

National Science Foundation, Grant IIP-1916535

Keywords and Phrases

Cascading theory; High-speed via model; Non-functional Pads (NFPs); Pad to anti-pad ratio optimization; Python-Based simulation

International Standard Serial Number (ISSN)

2158-1118; 1077-4076

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2025 Institute of Electrical and Electronics Engineers, All rights reserved.

Publication Date

01 Jan 2025

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