Abstract
High-K dielectric reduced surface field (RESURF) effects in high-voltage bulk FinFETs through three-dimensional simulation are discussed in this paper for the first time. Compared to a planar gate LDMOSFET where the length of the drift region is the same, dielectric RESURF significantly increases the optimal implant dose for the drift region to a higher value, although BV2/Ron,sp is similar. By using a high-K dielectric in the shallow trench isolation (STI) to further enhance the dielectric RESURF, the BV is increased and the Ron,sp is reduced, yielding a significantly improved BV2/Ron,sp, together with a better ON/OFF current ratio. However, with the insertion of the high-K STI, CGD is increased and a punch-through in the drift region caused by the depletion region occurs at a smaller VDS, which is consistent with theory. It is observed that the high-K dielectric RESURF also has an impact on the vertical breakdown, and care must be taken to achieve an optimal BV. The simulation results presented in this paper are of great importance for realizing a system-on-a-chip (SOC) based on advanced CMOS technologies.
Recommended Citation
C. H. Cheng et al., "On the Effects of High-K Dielectric RESURF in High-Voltage Bulk FinFETs," IEEE Journal of the Electron Devices Society, vol. 8, pp. 565 - 571, article no. 9099861, Institute of Electrical and Electronics Engineers, Jan 2020.
The definitive version is available at https://doi.org/10.1109/JEDS.2020.2997804
Department(s)
Electrical and Computer Engineering
Publication Status
Open Access
Keywords and Phrases
Dielectric RESURF; FinFET; high-K; STI
International Standard Serial Number (ISSN)
2168-6734
Document Type
Article - Journal
Document Version
Final Version
File Type
text
Language(s)
English
Rights
© 2025 The Authors, All rights reserved.
Creative Commons Licensing
This work is licensed under a Creative Commons Attribution 4.0 License.
Publication Date
01 Jan 2020
