Abstract
Because of the continued scaling of technology and supply-threshold voltage, leakage power has become more significant in power dissipation of nanoscale CMOS circuits. Therefore, estimating the total leakage power is critical to designing low-power digital circuits. In nanometer CMOS circuits, the main leakage components are the subthreshold, gate-tunneling, and reverse-biased junction band-to-band-tunneling (BTBT) leakage currents.
Recommended Citation
K. K. Kim et al., "Leakage Minimization Technique for Nanoscale CMOS VLSI," IEEE Design and Test of Computers, vol. 24, no. 4, pp. 322 - 330, Institute of Electrical and Electronics Engineers (IEEE), Jul 2007.
The definitive version is available at https://doi.org/10.1109/MDT.2007.111
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
Gate-Tunneling Current; Input Pattern Generation; Leakage Power; Nanometer CMOS; Subthreshold Leakage Current; Electron Tunneling; Tunneling (Excavation); Leakage Currents; Cell Characterization
International Standard Serial Number (ISSN)
0740-7475
Document Type
Article - Journal
Document Version
Final Version
File Type
text
Language(s)
English
Rights
© 2007 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
01 Jul 2007
