Abstract
This paper presents an impedance-matching network design with numerical modeling of the parasitic effects. A modeling tool CEMPIE (a Circuit Extraction approach based on a Mixed Potential Integral Equation formulation) is used to model the hoard-level parasitics of surface mount technology (SMT) resistors for impedance-matching networks. A 3-layer design of impedance-matching network with 0402 SMT resistors is implemented according to the modeling results. And its performance is demonstrated.
Recommended Citation
S. Luan et al., "The Design of a Lumped Element Impedance-Matching Network with Reduced Parasitic Effects Obtained From Numerical Modeling," Proceedings of the IEEE International Symposium on Electromagnetic Compatibility, 2004, Institute of Electrical and Electronics Engineers (IEEE), Aug 2004.
The definitive version is available at https://doi.org/10.1109/ISEMC.2004.1349960
Meeting Name
IEEE International Symposium on Electromagnetic Compatibility, 2004
Department(s)
Electrical and Computer Engineering
Research Center/Lab(s)
Electromagnetic Compatibility (EMC) Laboratory
Document Type
Article - Conference proceedings
Document Version
Final Version
File Type
text
Language(s)
English
Rights
© 2004 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
01 Aug 2004
