An Optimal Piece-wise Linear Strategy For Reference Voltage Variation In Time-based CMOS Imagers
Abstract
Time-based CMOS imagers are promising due to their high dynamic range and improved Signal-to-Noise Ratio (SNR) compared to conventional CMOS imagers. The illuminance on a pixel is encoded with the time that the pixel voltage drops below a global reference voltage. In order to guarantee that all pixels reach the reference voltage within one frame period, the reference voltage must be slowly varied. Thus far, there have been no systematic studies of the best reference voltage variation procedure for the continuous case. We formulate this optimization problem by considering the averaged SNR as the objective function and the required minimum time interval as the constraint. This formulation leads to a reasonable piecewise linear variation strategy. Finally, we also consider the effect of the non-zero comparator delay on this solution.
Recommended Citation
X. Qi and J. G. Harris, "An Optimal Piece-wise Linear Strategy For Reference Voltage Variation In Time-based CMOS Imagers," Proceedings of the IASTED International Conference on Circuits Signals and Systems, pp. 182 - 187, ACTA Press, Dec 2003.
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
CMOS image sensor; Comparator delay; Dynamic Range (DR); Signal-to-Noise Ratio (SNR); Well Capacity
International Standard Book Number (ISBN)
978-088986351-4
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2025 ACTA Press, All rights reserved.
Publication Date
01 Dec 2003
