Live Free or Die Hard: Design for Reliability in 3D Integrated Circuits
Abstract
In this chapter, we discuss the reliability issues about 3D-ICs fabrication process under technologies nowadays, and propose possible solutions to address the problems. In Section 9.1, we lay down the reasons in detail as to why there are seldom 3D-IC products today versus the problem of low yield of TSVs. Section 9.2 shows two major fault-tolerant structures, double TSV and shared-spare TSV, to improve the chip yield. The fault-tolerant design constraints then are addressed in Section 9.3. In Section 9.4, we address the problem of spare TSV assignment, and proposed two heuristics to optimize area overhead under given constraints. A fault-tolerance clock network then is discussed in Section 9.5 with two different structures. Concluding remarks are given in Section 9.6.
Recommended Citation
Y. G. Chen et al., "Live Free or Die Hard: Design for Reliability in 3D Integrated Circuits," Physical Design for 3D Integrated Circuits, pp. 193 - 227, Taylor and Francis Group; Taylor and Francis, Jan 2017.
The definitive version is available at https://doi.org/10.1201/b19225
Department(s)
Electrical and Computer Engineering
International Standard Book Number (ISBN)
978-149871037-4;978-149871036-7
Document Type
Article - Journal
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Taylor and Francis Group; Taylor and Francis, All rights reserved.
Publication Date
01 Jan 2017
