Abstract
As different chips are stacked together in 3D ICs, the power/ground (P/G) network simulation becomes more challenging than that of 2D cases. In this paper, we propose a hierarchical simulation method suitable for 3D P/G network (HS3DPG), which can ensure full parallelism and good scalability with the number of tiers. In the IR drop analysis, when there are 9 tiers, the hierarchical method can be 6.5 times faster than the direct full network simulation. The accuracy of HS3DPG has been verified by a 3D P/G network from the industrial design. Besides, we introduce the 'locality' property into HS3DPG to further simplify the simulation. Finally, HS3DPG is used to analyze the voltage distribution of a 3D P/G network with clustered TSVs. © 2013 IEEE.
Recommended Citation
S. Tao et al., "HS3DPG: Hierarchical Simulation for 3D P/G Network," Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 509 - 514, article no. 6509647, Institute of Electrical and Electronics Engineers, May 2013.
The definitive version is available at https://doi.org/10.1109/ASPDAC.2013.6509647
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
3D P/G network; Hierarchical simulation; Port equivalent model
International Standard Book Number (ISBN)
978-146733029-9
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Institute of Electrical and Electronics Engineers, All rights reserved.
Publication Date
20 May 2013
