Abstract
Conventional three-dimensional integrated circuits (3D ICs) stack multiple dies vertically for higher integration density, shorter wirelength, smaller footprint, faster speed and lower power consumption. However, the through-silicon-vias (TSVs) in die stacking based 3D ICs are large in size (>1um) and reduce the benefits that can be attained by the technology. In this paper, we will introduce a new fabrication process that facilitates monolithic 3D die integration and yields much smaller TSVs (~50 nm). We will also discuss various design benefits brought by the monolithic 3D IC technology.
Recommended Citation
H. Geng et al., "Monolithic Three-dimensional Integrated Circuits: Process and Design Implications," ECS Transactions, vol. 61, no. 6, pp. 3 - 10, IOP Publishing; The Electrochemical Society, Jan 2014.
The definitive version is available at https://doi.org/10.1149/06106.0003ecst
Department(s)
Electrical and Computer Engineering
International Standard Book Number (ISBN)
978-160768539-5
International Standard Serial Number (ISSN)
1938-5862; 1938-6737
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 IOP Publishing; The Electrochemical Society, All rights reserved.
Publication Date
01 Jan 2014
