Abstract
Dynamic voltage scaling (DVS) has been widely used to suppress power consumption in modern designs. The decision of optimal operating voltage at runtime should consider the variations in workload, process as well as environment. As these variations are hard to predict accurately at design time, various reinforcement learning based DVS schemes have been proposed in the literature. However, none of them can be readily applied to designs with graceful degradation, where timing errors are allowed with bounded probability to trade for further power reduction. In this paper, we propose a Q-learning based DVS scheme dedicated to the designs with graceful degradation. We compare it with two deterministic DVS schemes, i.e., a stepping-based scheme and a statistical modeling-based scheme. Experimental results on three 45nm industrial designs show that the proposed Q-learning based scheme can achieve up to 83.9% and 29.1% power reduction respectively with 0.01 timing error probability bound. To the best of the authors' knowledge, this is the first in-depth work to explore reinforcement learning based DVS schemes for designs with graceful degradation.
Recommended Citation
Y. G. Chen et al., "Q-learning based Dynamic Voltage Scaling for Designs with Graceful Degradation," Proceedings of the International Symposium on Physical Design, pp. 41 - 48, Association for Computing Machinery (ACM), Mar 2015.
The definitive version is available at https://doi.org/10.1145/2717764.2717765
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
Dynamic voltage scaling; Graceful degradation; Q-learning
International Standard Book Number (ISBN)
978-145033399-3
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Association for Computing Machinery, All rights reserved.
Publication Date
29 Mar 2015
