Abstract
Clock power contributes a significant portion of chip power in modern IC design. Applying multi-bit flip-flops can effectively reduce clock power. State-of-the-artwork performs multi-bit flipflop clustering at the post-placement stage. However, the solution quality may be limited because the combinational gates are immovable during the clustering process. To overcome the deficiency, in this paper, we propose multi-bit flip-flop bonding at placement. Inspired by ionic bonding in Chemistry, we direct flipflops to merging friendly locations thus facilitating flip-flop merging. Experimental results show that our algorithm, called FF-Bond, can save 27% clock power on average. Compared with state-of-the-art post-placement multi-bit flip-flop clustering, FF-Bond can further reduce 14% clock power. © 2013 ACM.
Recommended Citation
C. C. Tsai et al., "FF-bond: Multi-bit Flip-flop Bonding at Placement," Proceedings of the International Symposium on Physical Design, pp. 147 - 153, Association for Computing Machinery (ACM), Mar 2013.
The definitive version is available at https://doi.org/10.1145/2451916.2451955
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
Clock power; Multi-bit flip-flops; Placement; Timing
International Standard Book Number (ISBN)
978-145031867-9
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Association for Computing Machinery, All rights reserved.
Publication Date
24 Mar 2013
