Through-silicon-via Pairs Modelling Via Compressed Sensing

Abstract

Through-Silicon-Vias (TSVs) are the critical enabling technique for three-dimensional integrated circuits (3D ICs). While there are a few existing works in literature to model the electrical performance of TSVs, they are either for fixed geometry or in lack of accuracy. In this paper, we use compressed sensing technique to model the electrical performance of TSV pairs. Experimental results indicate that with an exceptionally small number of samples, our model has a maximum relative error of 3.70% compared with full-wave simulations over a wide range of geometry parameters and frequencies.

Department(s)

Electrical and Computer Engineering

International Standard Book Number (ISBN)

978-193414228-8

International Standard Serial Number (ISSN)

1931-7360; 1559-9450

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2024 Springer, All rights reserved.

Publication Date

01 Jan 2014

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