Abstract

LC resonant clock is an attracting option for low power on-chip clock distribution designs. However, a major limiting factor to its implementation is the large area overhead due to the conventional spiral inductors. On the other hand, idle through-silicon-vias (TSVs) in three-dimensional integrated circuits (3D ICs) can form vertical inductors with minimal footprint and little noise coupling with horizontal traces, particularly suitable for the application of LC resonant clock. However, due to the strict constraints on the location of idle TSVs, the use of the TSV inductor is limited by the constrained choices of its location, inductance and quality factor. Moreover, these TSV inductors can be in any orientation with any distance apart, thereby causing complicated coupling effects. In this paper, we present a novel scheme to opportunistically use idle TSVs to form inductors in LC resonant clock of 3D ICs for maximum power reduction. We formulate the problem and devise a greedy algorithm to efficiently solve it. Experimental results on a few industrial designs show that compared with the conventional resonant clock designs using spiral inductors, our scheme with TSV inductors can reduce the inductor footprint by up to 6.30x with the same power consumption. Especially these TSV inductors are formed by existing idle TSVs, so they essentially come for free. To the best of the authors' knowledge, this is the very first work to apply TSV inductors to the resonant CDN.

Department(s)

Electrical and Computer Engineering

International Standard Book Number (ISBN)

978-147996278-5

International Standard Serial Number (ISSN)

1092-3152

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2024 Institute of Electrical and Electronics Engineers, All rights reserved.

Publication Date

05 Jan 2015

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