Abstract

3-D integrated circuits (3-D ICs) make use of the vertical dimension for smaller footprint, higher speed, lower power consumption, and better timing performance. In 3-D ICs, the inter-Tier-via (ITV) is a critical enabling technique because it forms vertical signal and power paths. Accordingly, it is imperative to accurately and efficiently extract the electrostatic capacitances of ITVs using field solvers. Unfortunately, the cylindrical via shape presents major challenges to most of the existing methods. To address this issue, we develop a novel floating random walk (FRW) method by rotating the transition cube to suit the cylindrical surface, devising a special space management technique, and proposing accelerating techniques for structures with large-sized through-silicon-vias. Experiments on typical ITV structures suggest that the proposed techniques are up to hundreds of times faster than a simple FRW approach and the boundary element method-based algorithms, without loss of accuracy. In addition, compared with extracting the square-Approximation structures, the proposed techniques can reduce the error by 10 \times. Large and Mult dielectric structures have also been tested to demonstrate the versatility of the proposed techniques.

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

Capacitance extraction; floating random walk method; monolithic inter-Tier via (MIV); three-dimensional (3D) IC

International Standard Serial Number (ISSN)

0278-0070

Document Type

Article - Journal

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2024 Institute of Electrical and Electronics Engineers, All rights reserved.

Publication Date

01 Dec 2015

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