Backplane Channel Design Optimization: Recasting a 3Gb/s Link to Operate at 25Gb/s and Above

Abstract

We start with hardware verified interconnect models based on a 3Gb/s serial link. Stepwise recasting of this single ended link proceeds by peeling off the distortions introduced by lossy dielectric, via stubs, trace and via array cross-talk, and outdated connectors. Equalization schemes (4-tap FFE, 2-stage CTLE, 15-tap DFE) are then applied to demonstrate error-free NRZ signaling at 25Gb/s over the rehabilitated link.

Department(s)

Electrical and Computer Engineering

International Standard Book Number (ISBN)

978-162276645-1

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2024 Curran Associates, Inc., All rights reserved.

Publication Date

01 Dec 2012

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