Abstract
Three-dimensional integrated circuits (3D ICs) have drawn groundswell of interest in both academia and industry in recent years. However, the power integrity of 3D ICs is threatened by the increased current density brought by vertical integration. to enhance reliability, the locations of power/ground through-silicon-vias (P/G TSVs), which are used to deliver power/ground signals to different layers, must be carefully placed to minimize IR-drop. However, the currents in 3D ICs are not deterministic and exhibit both spatial and temporal correlations. in view of this, we propose a correlation based heuristic algorithm for P/G TSV placement. Unlike most existing works, the proposed algorithm does not need iterations of full-grid simulations. Thus, it is especially attractive for large designs with millions of nodes. Experimental results on TSMC 90nm industrial designs indicate that the proposed method can achieve up to 70% reduction in IR-drop compared with the current industry practice, which uniformly distributes P/G TSVs. © 2012 IEEE.
Recommended Citation
P. W. Luo et al., "Reliable Power Delivery System Design for Three-dimensional Integrated Circuits (3D ICs)," Proceedings - 2012 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2012, pp. 356 - 361, article no. 6296499, Institute of Electrical and Electronics Engineers, Oct 2012.
The definitive version is available at https://doi.org/10.1109/ISVLSI.2012.73
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
3D IC; correlation; IR drop; Through-Silicon-Via
International Standard Book Number (ISBN)
978-076954767-1
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Institute of Electrical and Electronics Engineers, All rights reserved.
Publication Date
29 Oct 2012
