Abstract
In this paper, an efficient cascaded microwave network approach is presented for power and signal integrity analysis of multilayer printed-circuit boards (PCBs) and advanced electronic packages with multiple signal traces, multiple power-ground plates, multiple vias, and external loads such as decoupling capacitors. Each parallel-plate pair, which consists of two consecutive conductor plates functioning as either power or ground in the PCBs or packages, is modeled as one individual microwave network. Equivalent circuits are used in the microwave network to model the vias, and a parallel-plate impedance matrix is formulated to account for the wave interactions between the vias and the boundary of the PCB or package. If signal traces are present in a plate pair, a modal decomposition and recombination approach is employed to model two associated modes: The transmission line mode for the signal traces, and the parallel-plate mode for the power-ground plate pair. the microwave networks for each plate pair are finally cascaded together by enforcing the continuity of the voltages and currents at the via clearance holes in the conductor plate shared by two consecutive plate pairs. Numerical validation reveals that the cascaded microwave network approach produces accurate simulation results with much less central processing unit time and memory requirements than 3-D full-wave approaches. © 2011 IEEE.
Recommended Citation
Z. Z. Oo et al., "Cascaded Microwave Network Approach for Power and Signal Integrity Analysis of Multilayer Electronic Packages," IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 1, no. 9, pp. 1428 - 1437, article no. 5975209, Institute of Electrical and Electronics Engineers; Electronics Packaging Society, Sep 2011.
The definitive version is available at https://doi.org/10.1109/TCPMT.2011.2143712
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
Cascaded microwave network; electronic package; modal decomposition and recombination; power and signal integrity; via circuit model
International Standard Serial Number (ISSN)
2156-3950
Document Type
Article - Journal
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Institute of Electrical and Electronics Engineers; Electronics Packaging Society, All rights reserved.
Publication Date
01 Sep 2011