Efficient Multiple-bit Retention Register Assignment for Power Gated Design: Concept and Algorithms
Abstract
Retention registers have been widely used in power gated design to store data during sleep mode. Since they consume much larger area and power than normal registers, it is imperative to minimize the total retention storage size. the current industry practice only replace all registers with single-bit retention ones, which significantly limits the design freedom and results in excessive area and power overhead. towards this, for the first time in literature, we propose the concept of multi-bit retention register, with which only selected registers need to be replaced. It can significantly reduce the number of bits that need to be stored and thus the area and leakage power, but needs several clock cycles for mode transition. in addition, an efficient assignment algorithm is developed to minimize the total retention storage size subject to mode transition latency constraint. Experimental results show that our framework on average can reduce the leakage power in sleep mode and the retention storage area by 66.03%, compared with the single-bit retention register based design. © 2012 ACM.
Recommended Citation
Y. G. Chen et al., "Efficient Multiple-bit Retention Register Assignment for Power Gated Design: Concept and Algorithms," IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD, pp. 309 - 316, article no. 6386628, Institute of Electrical and Electronics Engineers, Dec 2012.
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
Low power; power gating; retention register
International Standard Serial Number (ISSN)
1092-3152
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Institute of Electrical and Electronics Engineers, All rights reserved.
Publication Date
01 Dec 2012
