Abstract
Through-Silicon-Vias (TSVs) are the critical enabling technique for three-dimensional integrated circuits (3D ICs). While there are a few existing works in literature to model the electrical performance of TSVs, they are either for fixed geometry or in lack of accuracy. in this paper, we use compressed sensing technique to model the electrical performance of TSV pairs. Experimental results indicate that with an exceptionally small number of samples, our model has a maximum relative error of 3.94% compared with full-wave simulations over a wide range of geometry parameters and frequencies. © 2011 IEEE.
Recommended Citation
T. Wang et al., "Compressed Sensing based Analytical Modeling for through-Silicon-Via Pairs," Midwest Symposium on Circuits and Systems, article no. 6026430, Institute of Electrical and Electronics Engineers, Oct 2011.
The definitive version is available at https://doi.org/10.1109/MWSCAS.2011.6026430
Department(s)
Electrical and Computer Engineering
International Standard Book Number (ISBN)
978-161284857-0
International Standard Serial Number (ISSN)
1548-3746
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Institute of Electrical and Electronics Engineers, All rights reserved.
Publication Date
13 Oct 2011
