Fault Modeling and Testability of CMOS Domino Circuits
Abstract
Domino logic circuits have become prevalent in high performance IC's because they offer fast switching speeds and smaller area compared to that of static CMOS logic. However, testing such circuits is a challenge due to their susceptibility to noise and their unique circuit topology. the lack of an acceptable fault model for domino circuits contributes to the complexity of testing such circuits. This paper introduces preliminary results for a comprehensive fault model of a domino circuit. the paper discusses some testability techniques that could help understand the faulty behavior of such circuits. the observations in this work will be extended to complex dynamic circuits such as adders and multipliers.
Recommended Citation
W. K. Al-Assadi et al., "Fault Modeling and Testability of CMOS Domino Circuits," Proceedings of the 2005 International Conference on Computer Design, CDES'05, pp. 21 - 27, Institute of Electrical and Electronics Engineers Computer Society, Dec 2005.
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
CMOS domino circuits; Design-for-test; Dynamic logic; Fault modeling; Static logic; Testability
International Standard Book Number (ISBN)
978-193241554-4
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Institute of Electrical and Electronics Engineers Computer Society, All rights reserved.
Publication Date
01 Dec 2005