Development and Analysis of Defect Tolerant Bipartite Mapping Techniques for Programmable Cross-Points in Nanofabric Architecture
Abstract
Chemically Assembled Electronic Nanotechnology (CAEN) using bottom-up approach for digital circuit design has imposed new dimensions for miniaturization of electronic devices. Crossbar structures or Nanofabrics using silicon nanowires and carbon nanotubes are the proposed building blocks for CAEN, sizing less than 20 nm, allowing at least 1010 gates/cm 2. Along with the decrease in size, defect rates in the above architectures increase rapidly, demanding for an entirely different paradigm for increasing yields, viz. greater defect tolerance, because the defect rates can be as high as 13% or more. in this paper, we propose a non-probabilistic approach for defect tolerance and evaluate it in terms of its coverage for different sizes of fabric and different defect rates. © 2007 Springer.
Recommended Citation
M. V. Joshi and W. Al-Assadi, "Development and Analysis of Defect Tolerant Bipartite Mapping Techniques for Programmable Cross-Points in Nanofabric Architecture," Advances and Innovations in Systems, Computing Sciences and Software Engineering, pp. 289 - 294, Springer, Dec 2007.
The definitive version is available at https://doi.org/10.1007/978-1-4020-6264-3_52
Department(s)
Electrical and Computer Engineering
International Standard Book Number (ISBN)
978-140206263-6
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Springer, All rights reserved.
Publication Date
01 Dec 2007
