Design of a NULL Convention Self-Timed Divider

Author

Scott C. Smith, Missouri University of Science and Technology

Abstract

An unsigned 8-bit ÷ 4-bit delay-insensitive iterative divider is developed using the NULL Convention Logic paradigm. the divider is simulated using a 0.5μm CMOS process with static cells. the simulation of the initial design yielded an average cycle time of 75.92 ns with a transistor count of 4,721. a subsequent design increased throughput by 18%, while only increasing area by 2.7%.

Recommended Citation

S. C. Smith, "Design of a NULL Convention Self-Timed Divider," Proceedings of the International Conference on Embedded Systems and Applications ESA'04 - Proceedings of the International Conference on VLSI, VLSI'04, pp. 447 - 453, Institute of Electrical and Electronics Engineers, Dec 2004.

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

Asynchronous logic design; Computer arithmetic; Delay-insensitive circuits; Iterative divider; NULL Convention Logic (NCL)

International Standard Book Number (ISBN)

978-193241541-4

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2024 Institute of Electrical and Electronics Engineers, All rights reserved.

Publication Date

01 Dec 2004