Abstract
A reconfigurable logic element (LE) is developed for use in constructing a NULL Convention Logic (NCL) FPGA. It can be configured as any of the 27 fundamental NCL gates, including resettable and inverting variations, and can utilize embedded registration for gates with three or fewer inputs. the developed LE is compared with a previous NCL LE, showing that the one developed herein yields a more area efficient NCL circuit implementation. the NCL FPGA logic element is simulated at the transistor level using the 1.8V, 180nm TSMC CMOS process. Copyright 2007 ACM.
Recommended Citation
S. C. Smith, "Design of a Logic Element for Implementing an Asynchronous FPGA," ACM/SIGDA International Symposium on Field Programmable Gate Arrays - FPGA, pp. 13 - 22, article no. 1216922, Association for Computing Machinery, Oct 2007.
The definitive version is available at https://doi.org/10.1145/1216919.1216922
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
Asynchronous logic design; Delay-insensitive circuits; Field programmable gate array (FPGA); NULL convention logic (NCL); Reconfigurable logic
International Standard Book Number (ISBN)
978-159593600-4
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Association for Computing Machinery, All rights reserved.
Publication Date
02 Oct 2007
