Design for Test Techniques for Asynchronous NULL Conventional Logic (NCL) Circuits
Abstract
Conventional ATPG algorithms would fail when applied to asynchronous circuits due to the absence of a global clock and presence of more state holding elements that synchronize the control and data paths, leading to poor fault coverage. This paper presents three DFT implementations for the asynchronous NULL Conventional Logic (NCL) paradigm, with the following salient features: 1) testing with commercial DFT tools is shown to be feasible; 2) this yields a high test coverage; and 3) minimal area overhead is required. the first technique incorporates XOR gates for inserting test points; the second method uses a scan latch scheme for improving observability; and in the third scheme, scan latches are inserted in the internal gate feedback paths. the approaches have been automated, which is essential for large systems; and are fully compatible with industry standard tools. © 2007 Springer.
Recommended Citation
V. Satagopan et al., "Design for Test Techniques for Asynchronous NULL Conventional Logic (NCL) Circuits," Advances and Innovations in Systems, Computing Sciences and Software Engineering, pp. 451 - 456, Springer, Dec 2007.
The definitive version is available at https://doi.org/10.1007/978-1-4020-6264-3_78
Department(s)
Electrical and Computer Engineering
International Standard Book Number (ISBN)
978-140206263-6
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Springer, All rights reserved.
Publication Date
01 Dec 2007
