Completion-Completeness for NULL Convention Digital Circuits Utilizing the Bit-Wise Completion Strategy

Abstract

Delay-Insensitive paradigms, such as NULL Convention Logic (NCL), require an additional condition, referred to herein as Completion-Completeness, in order to ensure delay-insensitivity when the bit-wise completion strategy is used along with one or more components that are not complete with respect to all of their inputs. Completion-completeness requires that completion signals only be generated such that no two adjacent DATA wavefronts can interact within any combinational component. Correctly applying the bit-wise completion strategy to a circuit with input-incomplete components does not ensure completion-completeness; instead this may require either modifying one or more completion sets or changing the input-completeness of one or more input-incomplete components. Examples of completion-incompleteness, and their solutions, are shown when applying the bit-wise completion strategy to circuits utilizing input-incomplete components, for an array of and functions, the final stage of an unsigned multiplier, and the partial product generation for an unsigned multiplier.

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

Bit-wise Completion; Delay-Insensitive Circuits; Dual-Rail Logic; Input-Completeness; NULL Convention Logic (NCL)

International Standard Book Number (ISBN)

978-193241510-0

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2024 Institute of Electrical and Electronics Engineers Computer Society, All rights reserved.

Publication Date

01 Dec 2003

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