Abstract
Similar to the effects of software viruses, hardware can also be compromised by introduction of malicious logic into circuits to cause unwanted system behaviors. This can be done by changing or adding internal logic, in such a way that it is undetectable using traditional testing and verification tools and techniques. Therefore, the user of the circuit needs to decide whether it can be trusted, i.e., it only performs functions defined in the original circuit specification (no more and no less), before employing it in the system. in this paper, a preliminary methodology is proposed to model potential hardware threats in order to determine a circuit's trustability and provide guidance to malicious logic checking tools. © 2007 IEEE.
Recommended Citation
J. Di and S. C. Smith, "A Hardware Threat Modeling Concept for Trustable Integrated Circuits," 2007 IEEE Region 5 Technical Conference, TPS, pp. 65 - 68, article no. 4380353, Institute of Electrical and Electronics Engineers, Dec 2007.
The definitive version is available at https://doi.org/10.1109/TPSD.2007.4380353
Department(s)
Electrical and Computer Engineering
International Standard Book Number (ISBN)
978-142441280-8
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Institute of Electrical and Electronics Engineers, All rights reserved.
Publication Date
01 Dec 2007
