Design and Implementation of an FPGA based Processor for Compressed Images

Author

V. S. Balakrishnan
Hardy J. Pottinger, Missouri University of Science and TechnologyFollow
Fikret Ercal, Missouri University of Science and TechnologyFollow
Mukesh Agarwal

Abstract

This paper deals with the implementation of a systolic array architecture in hardware using FPGAs for processing compressed binary images without decompressing them. Specifically, run-length encoding (RLE) is used for compression. Processing images in compressed form provides a significant speedup in the computation. Using a systolic architecture and implementing it in hardware further increases the speed.

Recommended Citation

V. S. Balakrishnan et al., "Design and Implementation of an FPGA based Processor for Compressed Images," Proceedings of SPIE - The International Society for Optical Engineering, vol. 4118, pp. 108 - 118, Society of Photo-optical Instrumentation Engineers, Jan 2000.

Department(s)

Electrical and Computer Engineering

Second Department

Computer Science

International Standard Serial Number (ISSN)

0277-786X

Document Type

Article - Conference proceedings

Document Version

Final Version

File Type

text

Language(s)

English

Rights

© 2024 Society of Photo-optical Instrumentation Engineers, All rights reserved.

Publication Date

01 Jan 2000