Analog Chip Design with Mentor Graphics for Submission to the MOSIS Foundry Interface

Author

William Eatherton
Hardy J. Pottinger, Missouri University of Science and TechnologyFollow

Abstract

This paper presents the previously undocumented steps in CMOS analog chip design for MOSIS fabrication using the commercial Mentor Graphics tool set. The focus of the design process presented is achieving maximum correlation between simulation and testing. Two example designs are presented for illustration. The primary example is an inverting amplifier and the second is a voltage controlled oscillator.

Recommended Citation

W. Eatherton and H. J. Pottinger, "Analog Chip Design with Mentor Graphics for Submission to the MOSIS Foundry Interface," Midwest Symposium on Circuits and Systems, vol. 1, pp. 444 - 447, Dec 1994.

Department(s)

Electrical and Computer Engineering

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2024 The Authors, All rights reserved.

Publication Date

01 Dec 1994