Abstract
The green (low power) chip design demands dramatic thermal and electrical simulation capabilities. In this paper, a novel thermal simulation approach for automatic thermal modeling of very large problems is introduced. This methodology can be fully integrated with existing solvers for electrical simulations, and make it possible to analyze practical on-chip and packaging thermal problems using the existing electromagnetic tools and geometry definitions, with very small additional effort. Its various applications to BEOL (on-chip wiring), thermal guideline design, and 3D integration (for multiple chip stacks) thermal modeling are investigated in this paper. We will demonstrate this capability with an automatic modeling framework, ChipJoule, for representative cases. © 2008 IEEE.
Recommended Citation
L. Jiang et al., "Thermal Modeling Of On-chip Interconnects And 3D Packaging Using EM Tools," Electrical Performance of Electronic Packaging, EPEP, pp. 279 - 282, article no. 4675934, Institute of Electrical and Electronics Engineers, Dec 2008.
The definitive version is available at https://doi.org/10.1109/EPEP.2008.4675934
Department(s)
Electrical and Computer Engineering
International Standard Book Number (ISBN)
978-142442873-1
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Institute of Electrical and Electronics Engineers, All rights reserved.
Publication Date
31 Dec 2008
