Abstract
In this talk, we will introduce a novel methodology using existing electromagnetic modelling tools for interconnect and packaging structures to simulate and model the temperature distribution without major modifications to these tools or simulated structures. This methodology can easily be integrated with the chip technology information and frame an electrical circuit simulator into an automatic, template-based simulation and optimization flow. A new accurate closed-form thermal model is further developed to simplify unnecessary object details. The model allows an equivalent medium with effective thermal conductivity (isotropic or anisotropic) to replace details in non-critical regions accurately so that complex interconnect structures can be simulated at a system level. Using these techniques, we demonstrate the modelling capability of very complex on-chip interconnects, packaging, and 3D integration technologies. © 2010 IEEE.
Recommended Citation
L. Jiang et al., "Electrical Modelling Of Temperature Distributions In On-chip Interconnects, Packaging, And 3D Integration," 2010 Asia-Pacific Symposium on Electromagnetic Compatibility, APEMC 2010, pp. 625 - 628, article no. 5475701, Institute of Electrical and Electronics Engineers, Aug 2010.
The definitive version is available at https://doi.org/10.1109/APEMC.2010.5475701
Department(s)
Electrical and Computer Engineering
International Standard Book Number (ISBN)
978-142445621-5
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2024 Institute of Electrical and Electronics Engineers, All rights reserved.
Publication Date
02 Aug 2010
