Designing Layout-Timing Independent Quantum-Dot Cellular Automata (QCA) Circuits by Global Asynchrony

Abstract

The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synchronize data flows, and the way to power QCA cells, make the design of QCA circuits quite different from VLSI and introduce a variety of new design challenges and the most severe challenges are due to the fact that the overall timing of a QCA circuit is mainly dependent upon its layout. This fact is commonly referred to as the "layout = timing" problem. to circumvent the problem, a novel self-timed QCA circuit design methodology referred to as the Globally Asynchronous, Locally Synchronous (GALS) Design for QCA is proposed in this paper. the proposed technique can significantly reduce the layout-timing dependency from the global network of QCA devices in a circuit; therefore, considerably flexible QCA circuit design and floorplanning will be possible.

Department(s)

Electrical and Computer Engineering

Sponsor(s)

University of Missouri Research Board

Comments

This work is partly supported by University of Missouri Research Board Grant.

Keywords and Phrases

Floorplanning; Global Asynchrony Local Synchrony (GALS); Layout = Timing Problem; Place and Route; Quantum-Dot Cellular Automata (QCA); Data Flow Analysis; Data Transfer; Digital Integrated Circuits; Logic Design; Network Architecture; Semiconductor Quantum Dots; Circuit Design; Timing Problems; Cellular Automata

International Standard Serial Number (ISSN)

1383-7621

Document Type

Article - Journal

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2007 Elsevier, All rights reserved.

Publication Date

01 Sep 2007

Link to Full Text

Share

 
COinS