Development of a User Friendly Gate-Level Logic Simulator
Abstract
A Design of a Digital Logic Simulator is Developed and Presented. BASIC on an IBM Personal Computer using Interactive Graphics Tools is Employed to Make the Simulator Easy to Use. the Simulator Can Handle Gate Level Logic Circuits, and Can Be Used for Both Logic Verification and Fault Testing. Efficient and Correct Simulation in a User-Friendly Environment Was the Main Design Objective. Concepts of Interactive Computer Graphics Are Extensively Applied to Enable the Drawing of the Circuit. Menu Structures Have Been Used to Simplify the Interaction of User and Computer. the Foundation Has Been Laid for a Simulator that Uses Pattern Recognition for Circuit Data Acquisition. the Simulator Permits the Verification of the Logic of a Circuit Without Fault. the Design Also Includes Provision for Inserting Delays and Simulating to Detect Hazards. Test Sequences to Detect the Presence of Faults in the Circuit Can Be Generated using Deductive Simulation. the Design Provides a Reliable Basis for Further Research into Logic Simulation. © 1987.
Recommended Citation
P. D. Stigall and K. Shiv, "Development of a User Friendly Gate-Level Logic Simulator," Computers and Electrical Engineering, vol. 13, no. 3 thru 4, pp. 147 - 167, Elsevier, Jan 1987.
The definitive version is available at https://doi.org/10.1016/0045-7906(87)90009-7
Department(s)
Electrical and Computer Engineering
International Standard Serial Number (ISSN)
0045-7906
Document Type
Article - Journal
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2023 Elsevier, All rights reserved.
Publication Date
01 Jan 1987
