Abstract
Using the Architecture Design and Assessment System (ADAS), the Processor Level Architecture of an Example Computer System is First Represented as a Directed Graph. Then, a Method of Simulating Instruction Execution as a Sequence of Data Transfers between the Nodes of the Graph is Presented. the Simulation Methodology Provides Flexibility in Observing the Architecture Dynamically at the Processor Level. an Example Application for Functional Verification is Discussed. Development of Techniques to Convert Programs into Node Sequences And, to Assign Appropriate Delays to the Nodes is Necessary to Further Enhance the Applicability of the Methodology. Functional Verification and Performance Estimation through This Approach Can Instigate Early Design Tradeoffs and Reduce System Development Costs.
Recommended Citation
P. D. Stigall and R. Huggahalli, "An Architecture Level Simulation Methodology," ANSS 1991 - Proceedings of the 24th Annual Symposium on Simulation, pp. 240 - 253, Institute of Electrical and Electronics Engineers, Apr 1991.
The definitive version is available at https://doi.org/10.1109/simsym.1991.151511
Department(s)
Electrical and Computer Engineering
International Standard Book Number (ISBN)
978-081862169-7
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2023 Institute of Electrical and Electronics Engineers, All rights reserved.
Publication Date
01 Apr 1991
