The Multicore Architecture

Abstract

The multicore architecture has played a significant role in computer performance improvements since it was first introduced in the early 2000s [2]. It provides performance improvements due to multiple cores executing instructions concurrently supporting both instruction level parallelism and thread level parallelism. The performance improvement can be achieved at lower clock frequencies as compared to superscalar architectures, resulting in higher performance per Watt. Finally, multicore processors provide an advantage over multiprocessor systems as resources can be shared among the cores that would be duplicated on a multiprocessor system. The advantages of multicore architectures come at the expense of several challenges such as cache coherency and communication among the cores. This chapter is intended to address these architectural challenges and their potential solutions within the scope of the multicore architecture. Multicore architectures can be heterogeneous or homogeneous. In homogeneous architectures, as the name suggests, all the cores on the device are the same. In heterogeneous architectures, two or more cores on the device are different. Applications may benefit from different combinations of complex and simple cores. Different cores being used for different purposes in the design may provide a more efficient design. The benefits of each type of architecture will be articulated in this article. Cache coherency is an important challenge in the multicore architecture. One or more levels of cache are private to each core and one or more levels of cache are shared among the cores. This presents a cache coherency challenge that must be managed. Data that may be used by multiple cores may be stored or modified in one core's private cache. Multiple protocols exist to resolve this issue. Different methods will be presented and compared. As the number of cores has increased, the interconnection framework has become a bottleneck in the system. Communication is necessary between the cores cache memory to ensure cache coherence. This interconnection architecture was traditionally done using a bus. As the number of cores has increased, a bus is not able to efficiently support the traffic and is limiting the performance improvement obtained by adding cores. The Network on a Chip (NoC) architecture has shown to be a more efficient interconnection mechanism that is able to provide performance improvements as the number of cores is increased. The interconnection mechanism among the cores will be discussed. Finally, to take advantage of the concurrency available from the multicore architecture, software must be developed for parallel execution. Developing and implementing software for parallel execution is much different than developing software for sequential execution. The tools and techniques used to write parallel software will also be discussed. An overview of the multicore architecture is first discussed. Design issues encountered with the multicore architecture such as cache coherency, interconnection frameworks, and designing software for parallel execution are then examined.

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

Cache coherency; Interconnection architecture; Multicore architecture; Parallel software

International Standard Serial Number (ISSN)

0065-2458

Document Type

Article - Journal

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2023 Elsevier, All rights reserved.

Publication Date

01 Jan 2022

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