Abstract
This article investigates hardware implementation of hierarchical temporal memory (HTM), a brain-inspired machine learning algorithm that mimics the key functions of the neocortex and is applicable to many machine learning tasks. Spatial pooler (SP) is one of the main parts of HTM, designed to learn the spatial information and obtain the sparse distributed representations (SDRs) of input patterns. The other part is temporal memory (TM) which aims to learn the temporal information of inputs. The memristor, which is an appropriate synapse emulator for neuromorphic systems, can be used as the synapse in SP and TM circuits. In this article, a memristor-based SP (MSP) circuit structure is designed to accelerate the execution of the SP algorithm. The presented MSP has properties of modeling both the synaptic permanence and the synaptic connection state within a single synapse, and on-device and parallel learning. Simulation results of statistic metrics and classification tasks on several real-world datasets substantiate the validity of MSP.
Recommended Citation
X. Liu et al., "Memristor-Based HTM Spatial Pooler with On-Device Learning for Pattern Recognition," IEEE Transactions on Systems, Man, and Cybernetics: Systems, vol. 52, no. 3, pp. 1901 - 1915, Institute of Electrical and Electronics Engineers, Mar 2022.
The definitive version is available at https://doi.org/10.1109/TSMC.2020.3035612
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
Hierarchical temporal memory (HTM); memristor; neural networks; neuromorphic architecture; spatial pooler (SP)
International Standard Serial Number (ISSN)
2168-2232; 2168-2216
Document Type
Article - Journal
Document Version
Final Version
File Type
text
Language(s)
English
Rights
© 2023 Institute of Electrical and Electronics Engineers, All rights reserved.
Publication Date
01 Mar 2022
