Abstract

System-efficient electrostatic discharge (ESD) design (SEED) models of a diode and transient voltage suppressor (TVS) were developed to study their transient response in a high-speed input/output interface. Previously reported SEED models were improved to strengthen their convergence stability and facilitate accurate predictions over a wide range of conditions. These improvements were required to accurately capture the race conditions between the TVS and on-chip diode, where the diode's turn on may prevent turn on of the TVS. Simulations and measurements were performed to demonstrate the impact of the ESD pulse's rise time on race conditions. During a race, results showed the worst-case quasi-static diode current could be twice as high for long rise-time pulses than for short rise-times where the TVS does not turn on, and on-chip diode current may be larger at low test voltages than at high test voltages where the TVS does turn on. Adding a small passive impedance between the external TVS and the on-chip diode helps the TVS turn on and reduce the current through the on-chip diode by more than 50%. Similarly, lengthening the trace between the TVS and diode could reduce on-chip diode current by up to a factor of two.

Department(s)

Electrical and Computer Engineering

Keywords and Phrases

Electromagnetic immunity; electrostatic discharge (ESD); integrated circuit (IC); system efficient ESD design (SEED); system-level ESD; transient-voltage suppression

International Standard Serial Number (ISSN)

1558-187X; 0018-9375

Document Type

Article - Journal

Document Version

Final Version

File Type

text

Language(s)

English

Rights

© 2023 Institute of Electrical and Electronics Engineers, All rights reserved.

Publication Date

01 Aug 2022

Download

Full Text Link

Share

 
COinS