Root Cause Analysis for the Phase Noise of the Clock Generator

Abstract

The performance of the high-speed links in the electronic system is highly dependent on the quality of the clock signal, which can be quantified by phase noise. The phase noise represents the instabilities of the signal in the frequency domain by measuring the power at various offsets from the carrier frequency. The root cause for the phase noise of the clock output at the resonance frequency is analyzed and identified in this paper. The power supply, the heat sink, and the external crystal are the main sources of the phase noise. Spurious occurs at the frequency of the power rail in the measured phase noise. The heat sink over the chip induces the conductive coupling noise to the clock. The low-frequency bump in the phase noise plot turns out to be induced by the external crystal design of the clock. More attention should be paid to the ground routing of the external crystal to ensure the quality of the clock output.

Meeting Name

2021 IEEE International Joint Electromagnetic Compatibility Signal and Power Integrity and EMC Europe Symposium, EMC/SI/PI/EMC Europe 2021 (2021: Jul. 26-Aug. 13, Raleigh, NC)

Department(s)

Electrical and Computer Engineering

Research Center/Lab(s)

Electromagnetic Compatibility (EMC) Laboratory

Comments

National Science Foundation, Grant IIP-1916535

Keywords and Phrases

Clock Generator; Crystal Resonator; Ground Connection; Jitter; Phase Noise

International Standard Book Number (ISBN)

978-166544888-8

Document Type

Article - Conference proceedings

Document Version

Citation

File Type

text

Language(s)

English

Rights

© 2021 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.

Publication Date

13 Aug 2021

Link to Full Text

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