A Compensation Technique for Threshold Mismatch in Sub-Threshold Current Mirror
Abstract
A novel compensation method is proposed to eliminate the threshold mismatch in sub-threshold current mirror. The gate voltage of transistor pair in basic current mirror is modified through negative feedback loop during tuning phase, thereby compensates the threshold variation from imperfect fabrication process. The circuit is implemented and simulated with 1.8V supply using standard 0.18μm CMOS technology and it accomplishes less than 1% inaccuracy with ±5% threshold variation in the 500nA input current range. The presented approach provides an accurate and continuous current copy in a wide current range while still preserving the original structure of transistor pair, which means this technique can be implemented in various current mirror design without affecting its input and output characteristic.
Recommended Citation
Y. He et al., "A Compensation Technique for Threshold Mismatch in Sub-Threshold Current Mirror," Proceedings of the 2021 IEEE Microelectronics Design and Test Symposium (2021, Albany, NY), article no. 9476102, Institute of Electrical and Electronics Engineers (IEEE), May 2021.
The definitive version is available at https://doi.org/10.1109/MDTS52103.2021.9476102
Meeting Name
2021 IEEE Microelectronics Design & Test Symposium, MDTS 2021 (2021: May 18-21, Albany, NY)
Department(s)
Electrical and Computer Engineering
Keywords and Phrases
Current Mirror; Mismatch Compensation; Sub-Threshold Operation
International Standard Book Number (ISBN)
978-166542480-6
Document Type
Article - Conference proceedings
Document Version
Citation
File Type
text
Language(s)
English
Rights
© 2021 Institute of Electrical and Electronics Engineers (IEEE), All rights reserved.
Publication Date
21 May 2021
