IC Pin Modeling and Mitigation of ESD-Induced Soft Failures
In this article, electrostatic discharge (ESD) induced soft failures (SFs) of a USB3 Gen1 device are investigated by direct transmission line pulse injection with varying pulsewidth, amplitude, and polarity to characterize the failure behavior of the interface and to create a SPICE model of the voltage and current waveform dependent failure thresholds. ESD protection by transient-voltage-suppression diodes is numerically simulated in several configurations. The results show viability of using well-established hard failure mitigation techniques for improving SF robustness. A good agreement between numerical simulation for optimized board design and measurements are achieved. A novel concept of SF system efficient ESD design is proposed and demonstrated to be effective for making decisions during early product development, in board designing and prototyping phase.
G. Maghlakelidze et al., "IC Pin Modeling and Mitigation of ESD-Induced Soft Failures," IEEE Transactions on Electromagnetic Compatibility, vol. 63, no. 2, pp. 375-383, article no. 9203841, Institute of Electrical and Electronics Engineers (IEEE), Apr 2021.
The definitive version is available at https://doi.org/10.1109/TEMC.2020.3011544
Electrical and Computer Engineering
Keywords and Phrases
Circuit Model; Electrostatic Discharge (ESD); SEED; Soft Failure (SF); SPICE; Transmission Line Pulse (TLP)
International Standard Serial Number (ISSN)
Article - Journal
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01 Apr 2021